As the semiconductor industry approaches the limits of Moore's law, the demand for energy-efficient alternatives grows. The Single Flux Quantum (SFQ) superconducting logic family, based on integrated circuits (ICs) of thousands of niobium Josephson junctions operating at 4K, shows great promise as a developing technology for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic types are rapid single flux quantum (RSFQ), and its energy-efficient variant (ERSFQ). However, scaling SFQ circuits up to millions of junctions poses challenges, and the lack of industrial-strength design tools impedes their full potential. The recent IARPA SuperTools program aimed to develop an integrated electronic design automation (EDA) tool suite for superconductor electronics (SCE) for SFQ and adiabatic quantum flux parametron (AQFP) logic families.
This paper documents HYPRES’s efforts toward fully utilizing the EDA tool suite using the SFQ RTL-to-GDS flow, which is the comprehensive process of transforming SCE digital circuits’ register transfer level (RTL) description into a physical layout specification using a graphic design system (GDS), enabling chip fabrication. The RTL-to-GDS process involves several steps, including synthesis (converting RTL into gate-level representation), logical equivalence (verifying RTL and gate-level netlist), place and route (determining the physical locations of standard cell library on the chip, clock tree synthesis, and routing the interconnections), and ultimately generating the GDS file that contains the detailed layout information for chip fabrication. In this context, HYPRES has designed a standard cell library for SFQ circuits using Synopsys EDA tools for the superconducting niobium IC foundry at MIT Lincoln Lab (MIT-LL 100µA/µm2 SFQ5ee fab node). The SFQ standard cell library supports both RSFQ and ERSFQ logic families and enables seamless integration of Synopsys Fusion Compiler (Synthesis, Place, and Route tool) for RTL-to-GDS design flow by utilizing cell-to-cell passive transmission line (PTL) connection support. Each library cell is optimized for circuit parameter margins under statistical variations for various fabrication process parameters. Further, each library cell contains Verilog behavioral description to support digital hardware description language (HDL) simulation and timing characterization leading to the development of Liberty files.
The paper validates the Fusion Compiler tool using HYPRES designs of varying complexity, comparing the performance metrics of single-clocking and dual-clocking schemes, and presenting trade-offs in operating frequency, gate and junction count, chip area, and power dissipation. Fusion Compiler employs a row-based placement methodology and adopts an H-tree structure during clock tree synthesis with localized unstructured clock trees to minimize clock skew. The paper further discusses the challenges specific to the million-junction scaling of SFQ circuits.
This work marks a significant step towards commercializing superconductor electronics and demonstrating industry-grade design tools for SFQ circuits with greater than 1 million junctions. The seamless integration of SFQ technology into Synopsys EDA tools paves the way for very large-scale SFQ designs, leveraging the advantages of ultra-low power and high-speed functionality. Additional refinements are imperative to unlock the complete potential of EDA tools for SFQ circuits and broaden their capacities as fabrication processes advance.
This work was supported by the Office of the Director of National Intelligence, Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office under Contract W911NF-17-9-0001. The authors are grateful to Stephen Whiteley, Eric Mlinar, and Aaron Baker from Synopsys for their invaluable contributions to EDA tool development and for sharing insights into tool usage.